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SiliconJackets is open to Georgia Tech students of any major or experience level who are willing to put in the work.

subteams

Digital Design

The digital design team is responsible for implementing the chip’s architecture in RTL. Using SystemVerilog, members work on individual modules, collaborating with other members and subteams to make sure that the modules function correctly and meet performance targets.

Design Verification

The verification and emulation subteam makes sure that the design is functional before being manufactured. Because of the high upfront cost of a tapeout, it is important to use a variety of software simulation and hardware emulation techniques to guarantee performance before it is set in silicon.

Physical Design

Physical design transforms the RTL representation of the chip into an integrated circuit made of gates and interconnects. Working with a complex set of industry-relevant tools, physical design requires a great amount of problem solving to make sure we get the most out of our designs.

Analog Design

Not all designs can be made with just 1s and 0s. Analog Designers use circuit analysis principles to manually lay out designs interfacing with continuous voltage values.

onboarding

Overview

Onboarding runs once every Fall and Spring semester, and is open to all students currently enrolled at Georgia tech, undergrad and graduate.

To join the Digital Design, Design Verification, or Physical Design teams, you must complete the Digital onboarding.

To join Analog Design, you must complete the Analog onboarding.

All onboardings are 6 weeks long, and involve the submission of deliverables at specific deadlines.

Specific information regarding each round of onboarding is available in the SiliconJackets Discord server at the beginning of every semester.

Digital Onboarding

Digital onboarding consists of three deadlines; one for each subteam in the digital domain.

  • Digital Design: Design and implement a module in RTL given a problem statement and spec (2 weeks)
  • Design Verification: Formally validate the functionality of your module using a UVM-like framework (2 weeks)
  • Physical Design: Perform an implementation flow on your design using Synopsys Design Compiler and Cadence Innovus (2 weeks)

You must complete all three phases to join any team in the digital domain. Partial completion of the onboarding will not grant admission to the club, and partial completion does not carry over between semesters.

After you complete the onboarding project, you will indicate your team preference via a survey and be placed into a team accordingly.

Successful completion of the digital onboarding grants access to the digital subteams, but does not grant access to the analog subteam.

Analog Onboarding

The analog onboarding process is a single 6 week project, run in sync with the digital onboarding process.

In this onboarding, you will design and lay out an analog design given a spec and simulate it to ensure it meets performance targets.

Successful completion of the analog onboarding grants access to the analog subteam, but does not grant access to any digital subteams.

Questions? Connect with us!