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We welcome students of any level!
Our organization is not limited by year of study or major. We have members from freshman to PhD making meaningful contributions to our work from both inside ECE and elsewhere. Lookout for recruitment flyers and posts at the beginning of each semester!

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Design

The digital design team is responsible for implementing the chosen architecture in RTL. Using SystemVerilog, members work on individual modules, collaborating with verification and digital design to make sure that the modules function correctly and meet performance targets.

Verification

The verification and emulation holds the most important job of making sure that the design is functional before being manufactured. Because of the high upfront cost of a tapeout, it is important to use a variety of software simulation and hardware emulation techniques to guarantee performance before it is set in silicon.

Physical

Physical design holds the important task of transforming hardware representation in SystemVerilog into physical hardware in the real world. Working with a complex set of tools, physical design requires a great amount of problem solving to make sure we get the most out of our designs.